not_IO@lemmy.blahaj.zone to Programmer Humor@programming.devEnglish · 9 days agomegaboollemmy.blahaj.zoneimagemessage-square36linkfedilinkarrow-up1426arrow-down12file-text
arrow-up1424arrow-down1imagemegaboollemmy.blahaj.zonenot_IO@lemmy.blahaj.zone to Programmer Humor@programming.devEnglish · 9 days agomessage-square36linkfedilinkfile-text
minus-squareYorick@piefed.sociallinkfedilinkEnglisharrow-up21·9 days agoMay I introduce the VHDL STD library where you can set an output to “don’t care”: Wikipedia IEEE-1164 As an embedded electronics engineer discovering VHDL was a blast and a mindfuck!
minus-squarewhite_nrdy@programming.devlinkfedilinkarrow-up10·9 days agoDon’t worry, VHDL is still a mindfuck sometimes even after being an FPGA engineer for years (mostly only using VHDL). It’s such a cool language, and I am glad you discovered and are enjoying it!
May I introduce the VHDL STD library where you can set an output to “don’t care”:
Wikipedia IEEE-1164
As an embedded electronics engineer discovering VHDL was a blast and a mindfuck!
Don’t worry, VHDL is still a mindfuck sometimes even after being an FPGA engineer for years (mostly only using VHDL). It’s such a cool language, and I am glad you discovered and are enjoying it!